Gridded physical implementation of electronic design has been widely used. Nonetheless, the traditional gridded physical implementation is not correct-by-construction and fails to accommodate the trim mask rules. In addition, conventional physical design approaches are usually dependent upon the total number of shapes in a physical design. In other words, the larger the electronic design is, the longer it takes these conventional physical design tools to perform their respective functions. Regarding multiple-patterning to achieve half-pitch sizes in modern electronics (e.g., designs with 14 nm or 10 nm technology nodes), some previous solutions utilize multiple core masks; and some other previous solutions utilize self-aligned double patterning techniques. Both approaches have their own respective disadvantages and do not accommodate the trim mask rules. For design rule checking, conventional DRC (design rule checking) examines the shapes or geometries of a physical design, and the search time for each search of the conventional DRC is to be of an order(log(n)) or even an order(n) depending on the design database used for the DRC process, where n denotes the total number of shapes in the entire design.